PM=00, NMIC=0, GIPn=0, TEn=0, Fn=0, FUP=0, EP=0, RFn=0
Status Register
| Fn | For n = {0, 1, 2} Processor A/B Side Flag n 0 (0): Processor B/A Fn bit in the CR register is written 0 (default). 1 (1): Processor B/A Fn bit in the CR register is written 1. |
| NMIC | Processor A/B Non-Maskable-Interrupt Clear 0 (0): Default 1 (1): Writing “1” clears the NMI bit in the BCR register. |
| EP | Processor A/B Side Event Pending 0 (0): The Processor A-side event is not pending (default). 1 (1): The Processor A-side event is pending. |
| PM | Processor B/A Power Mode 0 (00): The Processor B/A is in Run Mode. 1 (01): The Processor B/A is in WAIT Mode. 2 (10): The Processor B/A is in STOP/VLPS Mode. 3 (11): The Processor B/A is in LLS/VLLS Mode. |
| FUP | Processor A/B Flags Update Pending 0 (0): No flags updated, initiated by the Processor A, in progress (default) 1 (1): Processor A/B initiated flags update, processing |
| TEn | For n = {0, 1, 2, 3} Processor A/B Transmit Register n Empty 0 (0): Processor A/B TRn register is not empty. 1 (1): Processor A/B TRn register is empty (default). |
| RFn | For n = {0, 1, 2, 3} Processor A/B Receive Register n Full 0 (0): Processor A/B RRn register is not full (default). 1 (1): Processor A/B RRn register has received data from Processor B/A TRn register and is ready to be read by the Processor A/B. |
| GIPn | For n = {0, 1, 2, 3} Processor A/B General Interrupt Request n Pending 0 (0): Processor A/B general purpose interrupt n is not pending. (default) 1 (1): Processor A/B general purpose interrupt n is pending. |